This invention relates to a resin encapsulating molding die for manufacturing a semiconductor device for use in encapsulating a semiconductor element within molded resin.
FIG. 5 illustrates one example of a lower molding die of a conventional resin encapsulating die with a lead frame placed thereon and FIG. 6 illustrates in section taken along line X-X' of FIG. 5. In these figures, it is seen that the lower molding die has formed therein a plurality of cavities 1 each connected through a sub-runner 3b to a runner 4 along which the molten encapsulating resin flows into the cavities 1. The sub-runners 3b are branched out from the runner 4 and each has a gate 3a formed in a gate portion 3 of the molding die. It is also seen that a lead frame 2 is placed on the mold die. The lead frame 2 has a plurality of die pads 8 on each of which a semiconductor chips 7 is bonded and electrically connected through gold wires 9. As shown in FIG. 6, the semiconductor chips 7 are positioned within the respective cavities 1 of the molding die.
In the conventional resin encapsulating molding die for manufacturing a semiconductor device as shown in FIGS. 5 and 6 the gate portion 3 and the cavity portion 1 are integral, one piece, or unitary structures. With this type of molding die, when a molding resin which contains a large amount of filler material, such as silica, is used, severe abrasion or wear is experienced at the gate 3, which is an injecting port for the mold resin, posing difficult control problems in melting the molding resin and the incomplete separation from the molding die as well as breakage of the gate occur.
FIGS. 7 and 8 are views useful in explaining this abrasion phenomenon, where FIG. 7 is a fragmental plan view of the gate portion of a conventional integral type molding die in which the cavity and the gate are integrally defined and FIG. 8 is a fragmental sectional view taken along line 8--8 of FIG. 7. With this type of integral, one piece molding die, since there is no step or discontinuity in the cross-section of the gate portion, no burr is formed by the leakage of the molten resin. However, it is not possible to replace the gate portion 3 alone when the gate portion 3 is worn. It is to be noted that, although the molding die shown in FIGS. 7 and 8 is different from that shown in FIGS. 5 and 6 in that the latter is a die for manufacturing a semiconductor device having pins on one side or two opposing sides thereof (SIP or DIP) whereas the former is a die for manufacturing a chip having the pins on its four sides thereof (QFP), they are the same as far as the above-discussed abrasion phenomenon of the mold die is concerned.
Accordingly, there has recently been proposed a gate piece type resin encapsulating mold die which allows only the gate portion 3 to be replaced with a fresh piece when the gate piece is worn.
FIGS. 9 to 11 illustrate a conventional resin encapsulating molding die of the gate piece type, where FIG. 9 is a fragmental plan view showing a gate piece and a cavity piece, FIG. 10 is a sectional view taken along line 10--10 of FIG. 9 and FIG. 11 is a fragmental perspective view of the conventional gate piece type resin encapsulating mold die. In these figures, the molding die comprises an upper die A and a lower die B which are illustrated in an swung open position for explanation purposes. The upper die A comprises an upper cavity piece 11 having formed therein an upper half of a mold cavity 1 and an upper gate piece 15 intimately fitted to the upper cavity piece 11 at one corner of the mold cavity 1 and having formed therein a gate portion 3 composed of a gate 3a and a sub-runner 3b.
The lower die B is similar to that of the upper die A and comprises a lower cavity piece 12 having formed therein a lower half of the mold cavity 1 and a lower gate piece 16 intimately fitted to the lower cavity piece 12 at the corner of the mold cavity 1. However, the lower gate piece 16 of the lower die B has no gate portion 3. When in use, as shown in dash lines in FIG. 11, a lead frame 1 on which the semiconductor chip 7 is mounted and wire-bonded is placed between the upper and the lower dies A and B and the upper and the lower dies A and B are closed to define a closed space around the semiconductor chip 7 and the wiring as well as the inner leads of the lead frame 1. Then, the molten encapsulating resin may be supplied under pressure through the runner 4 (FIG. 5) and the gate portion 3 within the cavity 1.
In this conventional resin encapsulating molding die of the gate piece type, since the gate portion 3 composed of a gate 3a and a sub-runner 3b is formed as the upper and lower gate pieces 15 and 16 separate from the upper and the lower cavity pieces 11 and 12, only the upper and the lower gate pieces 15 and/or 16 can be easily replaced without changing the larger cavity pieces 11 and 12 when the gate portion 3 of the gate pieces 15 and 16 are worn and damaged.
With the conventional resin encapsulating molding die of the gate piece type, however, a discontinuity or a step may quite easily be formed, due to machining and assembly tolerances, between the upper and the gate pieces 15 and 16 or between the mating surfaces of the cavity piece and the gate piece for sealing the gate runner portion 3 and the cavity piece 11 and 12 for sealing the outer periphery of the semiconductor package, so that a gap may be present between the upper and the lower gate pieces 15 and 16 and the lead frame 2 (see FIG. 10), resulting in easy formation of the burr due to the leakage of the molten resin through the gap between the dies.
More particularly, in the conventional gate piece type encapsulating molding die, the upper and the lower gate pieces 15 and 16 are engaged and assembled with the cavity piece as parts separate from the cavity piece, so that a gap which often causes resin burrs is formed between the cavity pieces and the gate piece. Since a molding resin having a low viscosity is being used in recent years for completely and stably encapsulating a small and thin semiconductor element having a fine and complex configuration, the burrs due to the discontinuity formed between the gate piece and the cavity piece are more frequently generated.
FIGS. 12 and 13 are views for explaining the above problems in more detail, where FIG. 12 is a fragmental plan view showing a resin burr 18 formed when the semiconductor element is resin encapsulated with the molding die shown in FIGS. 9 to 11, and FIG. 13 is a sectional view taken along line 13--13 of FIG. 12. As illustrated, the resin burrs 18 are formed around the outer leads 13 which become outer electrodes of the semiconductor device after resin encapsulation, so that the removal of the resin burrs 18 is very difficult. If the resin burrs 18 cannot be removed, the outer electrodes cannot be properly shaped at the time of the press forming the outer electrodes into a desired configuration after the resin encapsulation of the semiconductor element.